High-level Logic Synthesis Research Group

Current research interests include:

• New high-level synthesis methods starting with the behavioral specification and yielding a structural description for RTL design of special-purpose systems based on FPGA, EPLD or VLSI.
• New scheduling algorithms
• New algorithms for resource allocation.
• Pipelining and loop handling during the scheduling and allocation.
• Distributed control design and consructing the processor units from the structural description.
• Embedding the new high-level synthesis methods into commercial CAD tools.

Software development projects:

• WinSam high-level synthesis CAD tool.
• PIPE high-level synthesis CAD tool.
• Modul generator on structural level.
• Scheduling evalution tool.

Hardware resources:

• SUN 4 workstations,
• IBM PCs
• HP 9000/720 and 710 workstations

Software tools:

• CADENCE
• Viewlogic
• ABEL
• LOGiC
• VHDL Model TECHNOLOGY V-System

Team leader and contact person:

Dr. Sc. Arató,Péter , professor (arato@fsz.bme.hu)

Members:

• dr. Horváth, István, senior lecturer
• dr. Horváth, Tamás, senior lecturer
• Jankovits, István, PhD student
• Szigeti, Szabolcs, PhD student
• Sugár, Zoltán, PhD student
• Visegrády, Tamás, PhD student

Recent publications:

1. P. Arató, I. Béres, A. Rucinski, R. Davies, R. Torbert The SAM High-Level Synthesis Method for Pipelined Custom ASICs Proceedings of 4th Custom Circuits Conference 1993, Budapest, 149-158.
2. P. Arató, I Béres, A. Rucinski, R. Davies, R. Torbert A High-Level Datapath Synthesis Method for Pipelined Structures MICROELECTRONICS JOURNAL, England, Elsevier Advanced Tecchnology, Vol. 25, No. 3, May 1994, 237-247.
3. P. Arató Seminar über Spezielle Fragen zum Digitalentwurf Universität Karlsruhe Institut für Technik der Informationsverarbeitung Institutsbericht 1992, 38-39
4. P. Arató, I. Béres The SAM High-Level Synthesis Method TEMPUS Workshop on Computer Aided Methods Budapest, 1993
5. P. Arató High-Level Logic Synthesis Seminar at the Department of Electrical and Computer Engineering University of New Hampshire, USA, 1993. okt. 25.
6. P. Arató, I. Béres A High-level Synthesis Method for Pipelined ASICs Proceedings of the 4-th International Conference on Optimization Brasov, May, 1994. 291-309.
7. H. Fahner Analyse der Anwendbarkeit der Sprachen VHDL und C++ für Beschreibung und Logiksynthese im Verhaltensbereich. Universität Karlsruhe Institut für Technik der Informationsverarbeitung Master Thesis, Karlsruhe- Budapest, 1992
8. P. Arató A Data-Flow Model and Method for Optimizing the Pipeline Restarting Period Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 543-553.
9. I. Béres A Scheduling and Allocation Method Based on a Modified Force-Directed Algorithm Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 554-561.
10. I. Jankovits A Scheduling and Allocation Method Based on a Time-Scaled Algorithm Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 562-569.
11. T. Visegrády A Modified Force-Directed Scheduling Method Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 570-576.
12. Katalin Pásztor-Varga An Approach to the Allocation Problem of a Pipelined Model Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 577-585.
13. L. Kozma Synthesising Methods of Parallel Systems. An Overview Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 586-594
14. A. Rucinski, J. F. Santucci, R. Harrison Design and Test Environment in FPGA-Based Microelectronic System Proceedings of the 8-th Symposium on Computer and Microprocessor Applications Budapest, Oct. 12-14, 1994. 595-603
15. A. Rucinski, P. Arató, L. Pasma, J. Santucci Distributed Curriculum in Microelectronic System Proceedings of NATW'94 Europe Workshop, Nimes, 1994. jun.30-jul.1, L1-L7.
16. P. Arató, A. Rucinski, I. Jankovits Time Scaled High-Level Synthesis for Pipelined Data-Fow Structures Proceedings of NATW'94 Europe Workshop, Nimes, 1994. jun.30-jul.1, T1-T6
17. Z. Sugár, P. Arató, A. Rucinski Control Units for Pipelined Data-flow Structures University of New Hampshire, Department of Electrical and Computer Engineering, Technical Report, December 1994.
18. Sz. Szigeti, Z. Sugár, I. Jankovits, P. Arató PIPE: An Educational Software Tool for High-level Synthesis Proceedings of ATW'95 EUROPE Workshop, Cargese, Corsica July 7-8, 1995
19. A. Rucinski, P. Arató, L. Pasma, J. Santucci Distributed Curriculum in Microelectronic Systems Journal of Microelectronic System Integration, Plenum Press, New York Vol. 2, Num. 4, Dec. 1994. pp. 251-259.